Jianming Tong
jianming [dot] tong [at] gatech [dot] edu

Ph.D. at Georgia Tech starting from Spring 2021, Visitng Researcher at MIT, Student Researcher at Google

Advisor: Tushar Krishna

Main Developer for FEATHER , SUSHI

My research is funded by Qualcomm Innovation Fellowship and SRC Jump 2.0

FPGA and FHE Lead in Synergy Lab @ Gatech

CV  /  Google Scholar  /  GitHub  /  LinkedIn  /  ORCID

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Research Interest

My primary research area is Computer Architecture with major interest on full-stack optimizations—spanning software, systems, and hardware—aimed at enhancing both the efficiency and privacy of AI systems.
  • Model (Software): Fully Homomorphic Encryption (FHE) efficient non-linear approximation: [ MLSys'24]
  • System: Multi-query Serving - Latency/Accuracy Tradeoff Navigation: [ IEEE Micro'23][ MLSys'23]
  • Architecture (Hardware): Reconfigurable Flexible Accelerator with dataflow-layout coswitching [ ISCA'24]

  • More boarderly, I'm interested in following topics, welcome to reach out for potential collaboration.
  • On-Chip Network: [ GLSVLSI'21][ TOC'21]
  • ASIC/FPGA Accelerator: [ TVLSI'23][ IMS'23][ RadarConf'23][ IMS'22]
  • Software-hardware CoDesign: [ FPT'21][ IMS'23]
  • Side-channel Attack: [ SENSOR'23]
  • Multi-Agent Collaborative Exploration with Communication-Compute Balancing: [ ICRA'21]
  • News

    Leading Publications (* Equal Contribution)
    As Principal Contributor and Leading Author
    FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
    International Symposium on Computer Architecture (ISCA), Jun 2024.
    SmartPAF: Accurate Low-Degree Polynomial Approximation of Non-polynomial Operators for Fast Private Inference in Homomorphic Encryption
    In Proc of Seventh Conference on Machine Learning and Systems, (MLSys), May 2024.
    Hardware-Software co-design for real-time latency-accuracy navigation in tinyML applications
    (IEEE micro), Sep 2023.
    SUSHI: SUbgraph Stationary Hardware-software Inference Co-design
    In Proc of Sixth Conference on Machine Learning and Systems (MLSys), Jun 2023.
    ++Qualcomm Innovation Fellowship
    ++Best Poster Award (IAP2023@MIT)
    SMMR-explore: Submap-based multi-robot exploration system with multi-robot multi-target potential field exploration method
    IEEE International Conference on Robotics and Automation (ICRA), 2021. Oral

    Collaborative Publications (* Equal Contribution)
    As Collaborator or Mentor
    Real-time Digital RF Emulation – II: A Near Memory Custom Accelerator
    IEEE Transactions on Radar Systems (TRadar), Sep 2024.
    SNATCH: Stealing Neural Network Architecture from ML Accelerator in Intelligent Sensors
    IEEE SENSORS conference(SENSORS), Aug 2023.
    On Continuing DNN Accelerator Architecture Scaling Using Tightly-coupled Compute-on-Memory 3D ICs
    IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Jul 2023.
    FPGA-Based High-Performance Real-Time Emulation of Radar System using Direct Path Compute Model
    International Microwave Symposium (IMS), Jun 2023.
    A High Performance Computing Architecture for Real-Time Digital Emulation of RF Interactions
    In Proc of IEEE Radar Conference, (RadarConf), May 2023.
    A Configurable Architecture for Efficient Sparse FIR Computation in Real-time Radio Frequency Systems
    International Microwave Symposium (IMS), 2021.
    ac2SLAM: FPGA Accelerated High-Accuracy SLAM with Heapsort and Parallel Keypoint Extractor
    International Conference on Field-Programmable Technology (FPT), 2021. Full Paper
    PIT: Processing-In-Transmission with Fine-Grained Data Manipulation Networks
    IEEE Transactions on Computers (TOC), 2021.
    COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks
    Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI), 2020.
    Insight: Adding NoC between Mem-Cache-CPU for supporting Sorting, Ordering and Multicasting (SOM) could boost 25X CPU perfromance for matrix inversion.
    [abstract] [paper] [bibtex]

    Workshops
    A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
    Jianming Tong, Anirudh Itagi, Tushar Krishna
    ReLU-FHE: Low-cost Accurate ReLU Polynoimal Approximation in Fully Homomorphic Encryption Based ML Inference
    FastSwtich: Enabling Real-time DNN Switching via Weight-Sharing


    Education
    Georgia Institute of Technology, USA
    Ph.D. in Computer Science • Jan. 2021 to Present
    Advisor: Prof. Tushar Krishna
    Georgia Institute of Technology, USA
    MS. in Computer Science • Jan. 2021 to May 2024
    Advisor: Prof. Tushar Krishna
    Xi'an Jiaotong University, China
    B.E. in Electrical Engineering and Automation (EE) • Sep. 2016 to Jun 2020
    Advisor: Prof. Pengju Ren


    Experience
    Google, USA
    Student Researcher • Aug. 2024 to Present
    Host: Asra Ali
    Massachusetts Institute of Technology, USA
    Visiting Researcher • Sep. 2023 to Present
    Advisor: Prof. Tushar Krishna , Host: Prof. Arvind
    Rivos Inc., Mountain View CA
    Ph.D. Intern in Computer Architecture • May. 2023 to Aug 2023
    Pacific Northwest National Lab (PNNL), Battelle WA
    Research Intern in Computer Architecture • Jun. 2022 to Aug 2022
    Alibaba DAMO Academy, Beijing
    Research Intern in Fully Homormophic Encryption Accelerator • Jul. 2021 to Aug. 2021
    Tsinghua University, Beijing
    (Vitising Student) Research Assitant in Robotics • Aug. 2020 to Jan. 2021
    Advisor: Prof. Yu Wang

    Book
    On-chip Network (Chinese)
    Translator
    Abstract
    This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of-the-art research in on-chip networks. [purchase translated version] [English version -- Free for University] [obtain original version]
    On-chip Network Chinese Translation
    Honors and Awards
    ML and System Rising Star, USA • Jul. 2024
    DAC Young Fellow, USA • Apr. 2024
    Best Poster Award, USA • Sep. 2023
    Winner in Qualcomm Innovation Fellowship, USA • Jul. 2023

    Services
    Artifact Evaluation Committee in ASPLOS'24, USA • Jul. 2023
    Artifact Evaluation Committee in ISCA'24, USA • Feb. 2024
    Computer Architecture Student Association (CASA) , USA • Since Sep. 2023

    Life
    I love writing songs, playing piano, guitar, singing and fitting in. I'm available on major music distributor like Apple Music, Spotify, QQ music and NetEase etc (Search my name in platforms to find me XD). Some thing about me could be also found here
    [Apple Music] [Spotify] [QQ Music] [Netease Music] [Youtube] [Youtube - Magic Mushroom] [Bilibili - Magic Mushroom]
    Last Updated: Sep 17, 2024